Cambridge AS & A Level9608

Processor fundamentals

Computer Science 9608 Chapter Notes

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Processor fundamentals
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In this chapter

  1. 1The Von Neumann Architecture
  2. 2CPU Components: ALU and Control Unit
  3. 3Essential CPU Registers
  4. 4The System Bus: Data's Highway
  5. 5The Fetch-Decode-Execute Cycle
  6. 6Handling Interrupts

1. The Von Neumann Architecture

The Von Neumann architecture is the fundamental design for most modern computers. Its core idea is the 'stored program concept', which means that not only the data to be processed but also the program instructions themselves are held together in the same main memory. The Central Processing Unit (CPU) fetches these instructions and data from memory one after another to execute a program. This model has three main features: a single main memory for both data and instructions, a processor (CPU) that executes instructions, and a control unit that manages the sequential execution of these instructions.

Key term

Stored Program Concept: The principle that program instructions and the data they use are both stored in the same main memory, from where they are fetched by the CPU.

Examiner insight

Examiners look for a clear understanding that both instructions and data are held in the same memory, which is the defining feature of the Von Neumann architecture.

Common pitfall

Confusing the Von Neumann architecture with the Harvard architecture. The key difference is that Harvard architecture uses two separate memories, one for instructions and one for data.

Fun fact

John von Neumann, a Hungarian-American mathematician, first published this model in 1945. It was so influential that almost every computer you've ever used follows its basic principles.

Worked example 13 marks

Describe three key features of the Von Neumann architecture.

  1. 1
    1. A single main memory is used to store both program instructions and the data that those instructions will process. This is the core of the 'stored program concept'.
  2. 2
    1. The system has a Central Processing Unit (CPU) which is responsible for fetching instructions from memory and executing them.
  3. 3
    1. Instructions are fetched and executed sequentially, one after another. The Program Counter register is used to keep track of the address of the next instruction to be fetched.

Recap

  • Von Neumann architecture is based on the stored program concept.
  • Both program instructions and data are stored in the same main memory.
  • The CPU fetches and executes instructions sequentially from memory.
  • This architecture is the basis for most general-purpose computers today.
  • The main components are a processor, memory, and input/output devices.

Quick check

  1. What is the name of the principle where instructions and data are stored in the same memory?1 mark

2. CPU Components: ALU and Control Unit

The Central Processing Unit (CPU) is the 'brain' of the computer, and it has two main components: the Arithmetic Logic Unit (ALU) and the Control Unit (CU). The ALU is the calculator of the CPU. It performs all arithmetic operations (like addition and subtraction) and all logical operations (like AND, OR, and NOT comparisons). The Control Unit is the manager. It doesn't perform calculations but instead directs the flow of data within the CPU and to other parts of the computer. It fetches instructions from memory, decodes them, and then sends out control signals to the correct components (like the ALU) to execute them. The CU's operations are synchronised by a clock, and the speed of this clock (clock speed, measured in GHz) determines how many instructions the CPU can process per second.

Key term

Control Unit (CU): The component of the CPU that directs and coordinates the operation of the processor by fetching, decoding and managing the execution of instructions.

Examiner insight

Marks are often awarded for explaining *how* the Control Unit manages the processor, for example, by sending control signals to other components based on a decoded instruction.

Common pitfall

Simply stating the ALU does 'maths' is too vague. Students should specify arithmetic operations (e.g., addition, subtraction) and logical operations (e.g., AND, OR, XOR).

Fun fact

The first microprocessor, the Intel 4004 from 1971, had a clock speed of 740 kHz. A modern 4.0 GHz CPU is over 5,000 times faster!

Worked example 14 marks

Compare the functions of the Arithmetic Logic Unit (ALU) and the Control Unit (CU).

  1. 1
    1. The ALU performs calculations and logical decisions. For example, it carries out arithmetic operations such as addition and subtraction.
  2. 2
    1. It also performs logical operations such as AND, OR, and NOT, which are used for making comparisons and decisions.
  3. 3
    1. The Control Unit, in contrast, does not perform calculations. Its role is to manage the processor's operations. It fetches instructions from memory.
  4. 4
    1. The CU then decodes these instructions and sends control signals to other components, such as the ALU and registers, to carry out the instruction.

Recap

  • The CPU contains the Arithmetic Logic Unit (ALU) and the Control Unit (CU).
  • The ALU performs all arithmetic and logical operations.
  • The Control Unit directs the flow of data and manages the execution of instructions.
  • The CU uses the system clock to synchronise all processor activities.
  • Clock speed determines how many instruction cycles the CPU can perform per second.

Quick check

  1. Which component of the CPU would be used to determine if one number is greater than another?1 mark
  2. What is the role of the clock in the CPU?1 mark

3. Essential CPU Registers

Registers are small, extremely fast storage locations located directly within the CPU. They are used to temporarily hold data, instructions, or memory addresses that the CPU is actively working on. Because they are inside the CPU, accessing them is much faster than accessing main memory (RAM). There are several key special-purpose registers:

  • Program Counter (PC): This holds the memory address of the *next* instruction to be fetched.
  • Memory Address Register (MAR): This holds the address of the memory location that the CPU needs to access, either to read data from or write data to.
  • Memory Data Register (MDR): This is a two-way register. It holds the data that has just been read from memory or the data that is about to be written to memory.
  • Current Instruction Register (CIR): This holds the actual instruction that is currently being decoded and executed.
  • Accumulator (ACC): This is a general-purpose register used to store the results of calculations performed by the ALU.

Key term

Register: A small, high-speed storage location directly within the CPU, used to temporarily hold data, instructions, or addresses during processing.

Examiner insight

Students who can clearly state which register holds what type of information (address vs. data vs. instruction) and at what stage of the cycle, score highly.

Common pitfall

Mixing up the MAR and MDR. Remember: MAR holds the *address* (like a house number), while the MDR holds the *data* (like the letter for that house).

Worked example 15 marks

Explain three differences between the Memory Address Register (MAR) and the Memory Data Register (MDR).

  1. 1
    1. Function: The MAR holds the memory address of a location to be accessed, whereas the MDR holds the actual data or instruction that is being transferred to or from that memory location.
  2. 2
    1. Data Type: The MAR only ever holds memory addresses.
  3. 3
    1. In contrast, the MDR can hold either a piece of data to be used in a calculation or a program instruction.
  4. 4
    1. Data Flow: The MAR receives its input from the Program Counter (during a fetch) or from the address part of an instruction. It sends its output to the address bus.
  5. 5
    1. The MDR is connected to the data bus and has a two-way flow of information with main memory.

Recap

  • Registers are small, high-speed memory locations inside the CPU.
  • The Program Counter (PC) stores the address of the next instruction.
  • The Memory Address Register (MAR) stores the address for the next memory access.
  • The Memory Data Register (MDR) holds data being transferred to or from memory.
  • The Current Instruction Register (CIR) holds the instruction currently being executed.
  • The Accumulator (ACC) stores the results of ALU operations.

Quick check

  1. Which register holds the address of the next instruction to be fetched?1 mark
  2. Which register acts as a temporary holding area for data being transferred to and from memory?1 mark

4. The System Bus: Data's Highway

The system bus is a set of parallel electrical pathways that connects the major components of a computer system, like the CPU and main memory. It acts as a communication highway. It is divided into three separate buses:

  1. Address Bus: This carries memory addresses from the CPU to other components, such as main memory and I/O devices. It is a one-way (unidirectional) bus. The width of the address bus (the number of wires) determines the maximum amount of memory the CPU can address. For example, a 32-bit address bus can access 2^32 memory locations.
  2. Data Bus: This carries the actual data and instructions between the CPU, memory, and I/O devices. It is a two-way (bidirectional) bus because data needs to travel both to and from the CPU.
  3. Control Bus: This carries control signals and clock signals from the Control Unit to manage and synchronise activities across the system. It is also bidirectional, carrying signals like 'memory read', 'memory write', and interrupt requests.

Maximum Addressable Memory = 2^(Address Bus Width)

Key term

System Bus: A set of parallel wires connecting the processor, main memory, and other components, divided into the address bus, data bus, and control bus.

Examiner insight

Top answers explain the direction of data flow for each bus (unidirectional for address, bidirectional for data and control) and the consequence of bus width on system performance and capabilities.

Common pitfall

Forgetting that the address bus is unidirectional (CPU to Memory), while the data bus is bidirectional.

Worked example 14 marks

A processor has a 16-bit address bus and an 8-bit data bus. Explain what these two buses are used for and state the maximum amount of memory this processor can address.

  1. 1
    1. Address Bus Use: The 16-bit address bus is used by the CPU to specify the memory location it wants to read from or write to. It is unidirectional, sending addresses from the CPU to memory.
  2. 2
    1. Data Bus Use: The 8-bit data bus is used to transfer the actual data or instructions between the CPU and memory. It is bidirectional.
  3. 3
    1. Maximum Memory Calculation: The maximum number of unique addresses is determined by the width of the address bus. With a 16-bit address bus, the processor can access 2^16 unique memory locations.
  4. 4
    1. 2^16 = 65,536 locations. This is equivalent to 64 KiB (since 1 KiB = 1024 bytes).

Recap

  • The system bus connects the CPU, memory, and other components.
  • It is composed of the address bus, data bus, and control bus.
  • The address bus is unidirectional and carries memory addresses from the CPU.
  • The data bus is bidirectional and carries data and instructions.
  • The control bus is bidirectional and carries command and timing signals.
  • The width of the address bus determines the maximum addressable memory.

Quick check

  1. Which of the three buses is unidirectional?1 mark
  2. What does the width of the address bus determine?1 mark

5. The Fetch-Decode-Execute Cycle

The Fetch-Decode-Execute cycle is the fundamental process that a CPU performs to run a program. It continuously fetches an instruction from memory, decodes it to understand what to do, and then executes it. This happens millions or billions of times per second. We can describe the 'Fetch' stage precisely using Register Transfer Notation (RTN):

  1. Fetch: The CPU fetches the next instruction from main memory.
  • `MAR <- [PC]`: The address stored in the Program Counter (PC) is copied to the Memory Address Register (MAR).
  • `PC <- [PC] + 1`: The PC is incremented to point to the next instruction for the next cycle.
  • `MDR <- [[MAR]]`: The instruction at the memory location specified by the MAR is fetched and copied into the Memory Data Register (MDR).
  • `CIR <- [MDR]`: The instruction is copied from the MDR to the Current Instruction Register (CIR).
  1. Decode: The Control Unit decodes the instruction in the CIR. It splits the instruction into its opcode (the operation to perform) and operand (the data or address to be used).
  2. Execute: The decoded instruction is carried out. This might involve using the ALU for a calculation, loading data from memory, or jumping to a different part of the program.

MAR <- [PC]

PC <- [PC] + 1

MDR <- [[MAR]]

CIR <- [MDR]

Key term

Fetch-Decode-Execute Cycle: The fundamental sequence of operations performed by a CPU to process a single machine code instruction.

Examiner insight

Students who can accurately describe the fetch stage using register transfer notation (RTN) and explain what each step achieves demonstrate a deep understanding.

Common pitfall

Incorrectly ordering the steps of the fetch stage, especially forgetting to increment the PC *after* its content has been copied to the MAR, not before.

Worked example 14 marks

The fetch stage of the fetch-decode-execute cycle can be represented by a series of steps in register transfer notation. Explain the meaning of the statement: MDR <- [[MAR]]

  1. 1
    1. This statement describes the transfer of data from main memory into the Memory Data Register (MDR).
  2. 2
    1. The `MAR` part refers to the Memory Address Register, which currently holds the address of the memory location to be accessed.
  3. 3
    1. The inner square brackets `[MAR]` mean 'the contents of the MAR', which is the memory address itself.
  4. 4
    1. The outer square brackets `[[MAR]]` mean 'the contents of the memory location whose address is in the MAR'. This is the actual data or instruction at that address.
  5. 5
    1. The `<-` symbol means 'is copied into'.
  6. 6
    1. Therefore, the entire statement means: 'The data held at the memory address specified by the MAR is copied into the MDR'.

Recap

  • The CPU continuously performs the Fetch-Decode-Execute cycle.
  • The Fetch stage retrieves the next instruction from memory.
  • The Decode stage interprets what the instruction means.
  • The Execute stage carries out the instruction.
  • Register Transfer Notation (RTN) is used to describe data movement between registers.
  • The Program Counter is always incremented during the fetch stage.

Quick check

  1. In RTN, what does `PC <- [PC] + 1` signify?1 mark
  2. After the fetch stage, which register holds the instruction that needs to be decoded?1 mark

6. Handling Interrupts

An interrupt is a signal sent to the CPU that temporarily 'interrupts' the currently executing program. These signals can come from hardware (e.g., a key press, a mouse click, a printer error) or software (e.g., division by zero). Interrupts are essential for efficient computing, as they allow the CPU to deal with urgent events without having to constantly check the status of all devices. When an interrupt is detected, the CPU performs the following steps:

  1. It completes the current fetch-decode-execute cycle.
  2. It checks the priority of the interrupt. If it's a higher priority than the current task, it proceeds.
  3. It saves the contents of all its registers (PC, ACC, etc.) onto a special area of memory called the stack. This is like placing a bookmark in the current program.
  4. It loads the starting address of the relevant Interrupt Service Routine (ISR) into the Program Counter.
  5. The CPU then executes the ISR, which is a small program designed to handle that specific interrupt.
  6. Once the ISR is finished, the saved register values are restored from the stack, and the original program resumes exactly where it left off.

Key term

Interrupt: A signal sent to the processor by a hardware device or software program that causes the CPU to suspend its current activities and execute an interrupt service routine.

Examiner insight

Examiners reward answers that describe the full interrupt handling process, including saving the current state (context switch), running the ISR, and restoring the state to resume the original task.

Common pitfall

Thinking that an interrupt simply stops the processor. It's a controlled pause, not a crash; the processor's state is carefully saved so it can resume later without any data loss.

Fun fact

Without interrupts, your computer would have to use a process called 'polling', where it constantly asks every single device 'Have you got anything for me yet?'. This would be incredibly inefficient and slow!

Worked example 16 marks

A user is typing a document and presses a key. Explain how the processor handles this event using an interrupt.

  1. 1
    1. The keyboard controller sends an interrupt signal to the CPU via the control bus.
  2. 2
    1. At the end of the current F-D-E cycle, the CPU detects the interrupt signal.
  3. 3
    1. The CPU saves the state of the current program by pushing the contents of its registers (like the PC and Accumulator) onto the system stack.
  4. 4
    1. The CPU then loads the address of the keyboard's Interrupt Service Routine (ISR) into the Program Counter.
  5. 5
    1. The ISR is executed. This routine reads the keypress data from the keyboard's buffer and places the corresponding character code into a memory buffer for the word processing application.
  6. 6
    1. After the ISR completes, the CPU restores the saved state by popping the original register values from the stack.
  7. 7
    1. The original word processing program resumes execution, now able to access the new character that was typed.

Recap

  • An interrupt is a signal to the CPU that requires immediate attention.
  • Interrupts can be generated by hardware or software.
  • When an interrupt occurs, the CPU suspends its current task to handle the event.
  • The current state of the CPU (register contents) is saved to the stack.
  • An Interrupt Service Routine (ISR) is executed to handle the interrupt.
  • After the ISR finishes, the original task is restored and resumes.

Quick check

  1. Give one example of a hardware-generated interrupt.1 mark
  2. What is the name of the special program that runs in response to an interrupt?1 mark

End-of-chapter exercise

Test yourself on the whole chapter. Work through these before moving on.

  1. State the full names of the registers abbreviated as PC, MAR, and CIR.3 marks
  2. Explain the purpose of the accumulator.2 marks
  3. Describe the function of the data bus and the address bus, highlighting a key difference between them.4 marks
  4. The Control Unit and ALU are the two main components of the processor. Explain why both are necessary for program execution, detailing two distinct functions of each.6 marks
  5. Explain what is meant by the 'stored program concept' and name the computer architecture it is associated with.3 marks
  6. A computer's specification states it has a 3.2 GHz processor. Explain what '3.2 GHz' means in the context of the CPU's operation.3 marks
  7. Using Register Transfer Notation, write down the four main steps of the fetch stage of the fetch-decode-execute cycle.4 marks
  8. A computer system has an address bus of width 32 bits. Calculate the maximum possible memory capacity of this system. Give your answer in GiB and show your working.3 marks
  9. Describe the sequence of main steps taken by a processor when it receives a hardware interrupt.5 marks
  10. Explain the difference between the contents of the Memory Address Register (MAR) and the Memory Data Register (MDR) during the fetch cycle.4 marks

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